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김주영 전기및전자공학부 2009 5, 5, 1, 2, 1, 1, 1, 1, 1, 3, 5, 6, 4, 4, 2025
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테라 연구실 신호 무결성, SIP/PCB 디자인, 차세대 고대역폭 메모리, 고급 패키징 기술, 전력 무결성, 접지 무결성, 머신러닝, 기반 SI/PI 최적 설계, 전자기 간섭/정합성, 무선전력전송 김정호 (전기및전자공학부)
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멀티미디어 VLSI 연구실 멀티미디어 VLSI 디자인, 저전력 고속 회로 설계 김이섭 (전기및전자공학부)
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반도체 시스템 연구실 칩 설계, 네트워크 시스템, 건강 관리 시스템 인문 처리, 온 칩 유회준 (전기및전자공학부)
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Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.56, no.4, pp.1093 - 1104, 2021-04
SCOPUS 68

Keywords Architecture bit-scalability bit-serial operation deep learning (DL) deep neural network (DNN) energy-efficient SRAM hierarchical bitline in-memory processing near-memory processing non-von Neumann architecture processing-in-memory (PIM) architecture sparsity aware SRAM

Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks
Kim, Ji-Hoon ; Lee, Juhyoung ; Lee, Jinsu ; Heo, Jaehoon ; Kim, Joo-Young

초록	We present an energy-efficient processing-in-memory (PIM) architecture named Z-PIM that supports both sparsity handling and fully variable bit-precision in weight data for energy-efficient deep neural networks. Z-PIM adopts the bit-serial arithmetic that performs a multiplication bit-by-bit through multiple cycles to reduce the complexity of the operation in a single cycle and to provide flexibility in bit-precision. To this end, it employs a zero-skipping convolution SRAM, which performs in-memory AND operations based on custom 8T-SRAM cells and channel-wise accumulations, and a diagonal accumulation SRAM that performs bit- and spatial-wise accumulation on the channel-wise accumulation results using diagonal logic and adders to produce the final convolution outputs. We propose the hierarchical bitline structure for energy-efficient weight bit pre-charging and computational readout by reducing the parasitic capacitances of the bitlines. Its charge reuse scheme reduces the switching rate by 95.42% for the convolution layers of VGG-16 model. In addition, Z-PIM's channel-wise data mapping enables sparsity handling by skip-reading the input channels with zero weight. Its read-operation pipelining enabled by a readsequence scheduling improves the throughput by 66.1%. The Z-PIM chip is fabricated in a 65-nm CMOS process on a 7.568-mm(2) die, while it consumes average 5.294-mW power at 1.0-V voltage and 200-MHz frequency. It achieves 0.31-49.12-TOPS/W energy efficiency for convolution operations as the weight sparsity and bit-precision vary from 0.1 to 0.9 and 1 to 16 bit, respectively. For the figure of merit considering input bit- width, weight bit-width, and energy efficiency, the Z-PIM shows more than 2.1 times improvement over the state-of-the-art PIM implementations.
서지사항	IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.56, no.4, pp.1093 - 1104, 2021-04
ISSN	0018-9200
주제분야	Engineering
저자 키워드	Architecture bit-scalability bit-serial operation deep learning (DL) deep neural network (DNN) energy-efficient SRAM hierarchical bitline in-memory processing near-memory processing non-von Neumann architecture processing-in-memory (PIM) architecture sparsity aware SRAM
DOI	10.1109/JSSC.2020.3039206
자료유형	Article; Proceedings Paper
기관	KAIST

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저널논문

Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks Kim, Ji-Hoon ; Lee, Juhyoung ; Lee, Jinsu ; Heo, Jaehoon ; Kim, Joo-Young

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Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks
Kim, Ji-Hoon ; Lee, Juhyoung ; Lee, Jinsu ; Heo, Jaehoon ; Kim, Joo-Young